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orangecrab

Here are 2 public repositories matching this topic...

niw / chisel_test

A simple Chisel test project for myself to learn Chisel and FPGA.

scala fpga chisel3 verilog tinyfpga orangecrab

Updated Nov 8, 2021
Scala

supleed2 / EIE4-FYP

Source files and notes of my Final Year Project, as part of an MEng in Electronics and Information Engineering from Imperial College London

embedded-systems systemverilog can-bus audio-synthesis risc-v cordic litex ecp5 waveform-generator vexriscv orangecrab stacksynth

Updated Jan 19, 2024
Python

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