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Updated
May 3, 2024 - Verilog
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32bitprocessor
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Hardware-synthesizable RV32I single-cycle core in strict Verilog-2001, modeled after Harris & Harris. Implemented on Artix-7 (125 MHz) with dual-port LUTRAM regfile, zero timing violations, and an interactive schematic viewer.
fpga rtl verilog isa vivado computer-architecture gtkwave instruction-set-architecture risc-v iverilog xilinx-vivado rv32i digital-logic-design cpu-design artix-7 single-cycle-processor singlecycle-datapath singlecycle 32bitprocessor verilog-2001
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Updated
Oct 2, 2026 - Verilog
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