This repository contains lab implementations using Verilog, ModelSim, Logisim, and RISC-V assembly in Venus. Each lab is organized in its own folder with source files and a README describing the tasks, concepts, and tools.
| Lab | Topic | Status |
|---|---|---|
| Lab 01 | Basic Logic Gates, XOR and 1's Complement | Completed |
| Lab 02 | Combinational Circuits | Completed |
| Lab 03 | Behavioral Modeling of Combinational Circuits | Completed |
| Lab 04 | RISC-V Assembly Fundamentals | Completed |
| Lab 05 | RISC-V Control Instructions and Loops | Completed |
| Lab 06 | RISC-V Procedures and Recursion | Completed |
| Lab 07 | Arithmetic Logic Unit (ALU) Design | Added |
| Lab 08 | Program Counter and Instruction Memory | Added |
| Lab 09 | Register File Design | Added |
| Lab 10 | To be added | Pending |
| Lab 11 | To be added | Pending |
| Lab 12 | To be added | Pending |
| Lab 13 | To be added | Pending |
- ModelSim for Verilog compilation and simulation
- Logisim for digital circuit design and simulation
- Venus for RISC-V assembly execution
Open the README inside a lab folder for its task list, source-file map, and instructions for running the work.