Industrial engineer with a background in FPGA/VHDL and embedded systems, with experience as a project/program manager in the space sector. Now working to transition to the software / embedded industry as an individual contributor or as a project manager โ while also still coding and building side projects.
Pinned Loading
-
hdlsnip.nvim
hdlsnip.nvim PublicParameterised VHDL templates for Neovim โ entities, FSMs, CDC, AXI4-Lite and testbenches, rendered from Lua rather than pasted.
VHDL 5
-
frame-extractor
frame-extractor PublicPython script to extract all frames from a video, powered by ffmpeg.
Python 1
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.


