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e2e: ADC sample-rate test survives a loopback that reads 0 V at the ADC's range edge - #66
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…DC's range edge test_adc_sample_rate_matches_the_host_clock failed on benchpod-c2f662 (analog module with the quad DAC) with "the ADC really samples at 4591 Hz (0.0115x the reported 400000 Hz)", on 3.10.0 and 3.10.1 alike. There the cal1 loopback reads 0 V at the top of the ADC code range: noise wraps between 65535 and 0, so 40 of 400 flat blocks had a 65535-count swing, counted as DAC bursts, and the fitted rate collapsed. The swing is now taken around each block's median, modulo 65536; the 5 kHz burst (about 1600 counts) is unchanged. A pod where the DAC never reaches the ADC skips instead of failing. On benchpod-c2f662: 3 of 3 passed. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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test_adc_sample_rate_matches_the_host_clockfailed on benchpod-c2f662 (analog module with the quad DAC) on fw 3.10.0 and 3.10.1 alike: "the ADC really samples at 4591 Hz (0.0115x the reported 400000 Hz)".Cause: on that module the internal
cal1loopback reads 0 V at the top of the ADC code range. Noise wraps between 65535 and 0, so flat blocks showed a 65535-count swing and counted as DAC bursts (40 of 400 with the DAC at 0 V), and the fitted rate collapsed. No external wiring is involved.Fix: each block's swing is taken around its own median, modulo 65536; the 5 kHz burst (~1600 counts) is unchanged. If no burst reaches the ADC at all, the test skips instead of failing.
On benchpod-c2f662: 3 of 3 passed.
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