Open-source high-performance RISC-V processor
Scala 7.4k 968
Documentation for XiangShan
Markdown 448 153
Open-source high-performance non-blocking cache
Scala 102 40
Modern co-simulation framework for RISC-V CPUs
C++ 191 113
XiangShan Frontend Develop Environment
Shell 73 77
Super fast RISC-V ISA emulator for XiangShan processor
C 352 147
A fork of Xiangshan for AI
A fork of XSCache for XSAI. Supports High-Bandwidth L2 Cache design.
Open-source L2 (RN) & LLC (HN) cache for XiangShan open-source RISC-V core. Supports CHI Issue B/C/E.b protocols.