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SIMD portability fixes, AVX-VNNI tier gate, reproducible BF16 check, README truth refresh - #341
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The AVX-512, scalar, wasm and nightly F64x8 carried all six lane compares; AVX2 and NEON carried only simd_ge/simd_le, so code using simd_eq/ne/lt/gt compiled on AVX-512 hosts and failed to compile on AVX2 and aarch64. The four additions follow the existing ge/le form in each file and the AVX-512 predicates: eq/lt/gt ordered (false on NaN), ne unordered (true on NaN), +0.0 == -0.0. simd-masking-parity gains check group 0xExx: all six relations over every pair of 16 IEEE edge values (NaN incl. negative and payload NaN, +-0, +-inf, MAX/MIN, MIN_POSITIVE, smallest subnormal), against plain scalar f64 operators, read back through select() so no backend mask layout is assumed. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01HdJxpkHATkdNL2veorKao2
…BUSD
Two coupled defects in the 256-bit u8xi8 VNNI tier:
1. The kernel (simd_amx::vnni2_dot_u8_i8) called _mm256_dpbusd_epi32, which
is the AVX-512VNNI+VL intrinsic and compiles to EVEX vpdpbusd (62 prefix,
verified by objdump). The tier is only selected when avx512f is absent,
so on every host it was selected for, the kernel would raise #UD.
It now calls _mm256_dpbusd_avx_epi32 (VEX, c4 prefix) under
target_feature avx2,avxvnni.
2. The tier was gated on avxvnniint8 (VPDPBSSD/VPDPBUUD), not on avxvnni,
the feature VEX VPDPBUSD needs. Alder Lake has AVX-VNNI but not
AVX-VNNI-INT8, so cpu_tier_for_cpu("alderlake") said avxvnni while the
runtime ladder picked avx2_fma.
SimdCaps gains an avxvnni field (is_x86_feature_detected!("avxvnni")).
The gate is changed at all four dispatch sites: cpu_ops, vnni_dot,
simd_amx::matvec_dispatch and the burn matmul ladder.
cpu_ops' ladder is factored into select_cpu_ops(caps, amx_os_ok) so it can
be tested on synthetic capability sets: Alder Lake, Arrow Lake, an
int8-only set, Haswell, Cascade Lake and Sapphire Rapids. A direct
kernel-vs-scalar test runs only on AVX-VNNI hosts and prints SKIPPED
otherwise.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01HdJxpkHATkdNL2veorKao2
…inputs Compares simd::f32_to_bf16_batch_rne bit-for-bit against the scalar reference and an independent f64 nearest-value oracle (SDM VCVTNEPS2BF16 semantics: quiet-forced NaN with sign and top payload, DAZ to signed zero, ties to even, overflow to infinity at the 2^128 midpoint). Prints the batch path, thread count, chunk size, inputs covered, both mismatch counts, an order-independent output checksum and elapsed time; exits 1 on any mismatch. Measured here (Xeon, Cascade Lake class, AVX-512F path, rustc 1.98.1, 4 threads): 4294967296 inputs, 0 / 0 mismatches, checksum 0x5cd3eaa07f7f8080 (identical with 2 threads), 11.5 s. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01HdJxpkHATkdNL2veorKao2
Every quantitative claim now carries an evidence class; the Evidence table names host, toolchain and method. - Counts refreshed at f2c1aea: 100 hpc modules (was 55), 2,534 lib tests (was 880), Rust 1.98.1 (was 1.94), ~205k added lines / 424 files. - Corrected: Fingerprint<256> is 2,048 bytes, not 32; TDPBUSD is 16,384 MACs per instruction, not 256. - Measured on this host: palette lookup 0.84 ns, Base17 L1 3.04 ns, 1M x 32 B Hamming sweep 15.5 ms, SIMD ratios against named baselines, GEMM, f16 transcoding. Withdrawn: per-platform rates, FAISS/GPU comparisons, the GEMM fork-vs-upstream table and the tok/s table (no benchmark here). - AMX 169.7 GMAC/s is attributed to Emerald Rapids (AMX_GOTCHAS.md), not this host. - BF16 exhaustive claim now points at examples/bf16_rne_exhaustive.rs with method, checksum and time. - Lance integration: the cascade does not replace lance-linalg inside a Lance scan; lance-graph exposes Hamming as a DataFusion UDF and rejects it in Lance ANN. - Notes the avxvnni tier gate and that it was not executable here. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01HdJxpkHATkdNL2veorKao2
The German page still carried the withdrawn numbers (55 modules, 880 tests, Rust 1.94, the per-platform and GEMM tables). It is now a translation of README.md: same numbers, tables, commands and links; the Evidence section is 'Belege fuer die Zahlen auf dieser Seite'. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01HdJxpkHATkdNL2veorKao2
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📝 WalkthroughWalkthroughThe changes add exhaustive BF16 conversion checks, update AVX-VNNI runtime detection and dispatch, add F64x8 comparison methods and parity checks, and revise README claims and supporting evidence. ChangesBF16 validation and documentation
AVX-VNNI detection and dispatch
F64x8 comparisons
Priority: ⬇️ Low Estimated code review effort: 4 (Complex) | ~45 minutes Change: Bug fix Suggested reviewers: Merge Risk: 🟡 Moderate · up to Gate the AVX-VNNI tier on FMA before merging to avoid an unsupported-instruction trap on affected hosts. Correct and clarify the benchmark figures in both READMEs. 🚥 Pre-merge checks | ✅ 5✅ Passed checks (5 passed)
✨ Finishing Touches📝 Generate docstrings
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- simd-masking-parity: the F64x8 anti-vacuity line compared NaN to itself, which -D warnings (config-v4) rejects as invalid_nan_comparisons. Keep only the meaningful check that all 256 edge pairs ran. - examples/bf16_rne_exhaustive needs required-features = ["std"]: ndarray::simd is std-gated and the tests job builds --no-default-features. Reproduced locally: the config-v4 parity build and cargo test -p ndarray --no-default-features --no-run both pass. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01HdJxpkHATkdNL2veorKao2
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Inline comments:
Review comments at @README.md:
- Line 67: Update the rounded 32-byte-row sweep rate to 2.1 GB/s in README.md at
line 67 and README-DE.md at line 67, keeping the stated row count and duration
unchanged.
- Around line 87-91: Update the benchmark descriptions in both the English and
German sections of README.md to clarify that each timing pair lists the fork
result first and the baseline result second. Leave the timing values and table
contents unchanged.
Review comments at @src/simd_runtime/cpu_ops.rs:
- Line 221: Update the AVX-VNNI selection condition in cpu_ops() to also require
_caps.fma before returning CPU_OPS_AVXVNNI, so machines without FMA cannot
select kernels that execute FMA instructions. Add coverage for the
avx2-and-avxvnni-without-fma case to verify it does not select that table.
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Cargo.tomlREADME-DE.mdREADME.mdcrates/burn/src/ops/matmul.rscrates/simd-masking-parity/src/lib.rsexamples/bf16_rne_exhaustive.rssrc/simd_amx.rssrc/simd_avx2.rssrc/simd_caps.rssrc/simd_neon.rssrc/simd_runtime/cpu_ops.rssrc/simd_runtime/vnni_dot.rs
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…ng order The avxvnni CpuOps table's add_mul pointers are AVX2+FMA kernels, but AVX-VNNI does not imply FMA, so a CPU (or hypervisor mask) reporting avx2+avxvnni without fma would have selected FMA code. The gate now requires fma; tier_ladder_gates_on_the_kernel_feature covers the no-FMA case (falls to scalar). README/README-DE: 1,000,000 x 32 B / 15.5 ms is 2.06 GB/s, so 2.1 not 2.2; state that each timing pair lists the fork first. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01HdJxpkHATkdNL2veorKao2
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Five commits, each its own slice.
Correctness
F64x8 comparisons on AVX2 and NEON (
72f86af)simd_eq/simd_ne/simd_lt/simd_gtexisted on AVX-512, scalar, wasm and nightly, but not on AVX2 or NEON. Code using them compiled on AVX-512 hosts and failed to compile elsewhere. The four methods are now added on both.eq,ltandgtare ordered (false on NaN),neis unordered (true on NaN), and+0.0 == -0.0.simd-masking-paritygains check group0xExx: all six relations over every pair of 16 IEEE edge values, compared with plain scalarf64operators and read back throughselect().config-v3), NEON (qemu), wasm and wasm-scalar.simd_avx2.rsthe AVX2 arm fails to compile, and a deliberately wrongsimd_nefails with code0xe01.avxvnnitier (59f89d2). Two defects:simd_amx::vnni2_dot_u8_i8called_mm256_dpbusd_epi32, which is the AVX-512VNNI+VL intrinsic. objdump confirms it emits EVEXvpdpbusd(62prefix). The tier is only selected whenavx512fis absent, so on every host it is selected for the instruction raises #UD. It now uses_mm256_dpbusd_avx_epi32(VEX,c4prefix) underavx2,avxvnni.avxvnniint8(VPDPBSSD/VPDPBUUD) instead ofavxvnni. Alder Lake has AVX-VNNI but not AVX-VNNI-INT8, so the runtime ladder pickedavx2_fmawhilecpu_tier_for_cpu("alderlake")reportedavxvnni.Changes:
SimdCaps::avxvnnifield.cpu_ops,vnni_dot,matvec_dispatch, and the burn matmul.select_cpu_ops(caps, amx_os_ok)and tested on synthetic Alder Lake, Arrow Lake, int8-only, Haswell, Cascade Lake and Sapphire Rapids capability sets. With the old gate the test fails (left: "avx2_fma", right: "avxvnni").Not verified by execution: the VEX kernel. The test host is Cascade Lake, where VEX
vpdpbusdraises SIGILL, and qemu TCG reportsdoesn't support requested feature: avx-vnni. A kernel-vs-scalar test runs only on AVX-VNNI hosts and printsSKIPPEDotherwise.crates/burnfails to build on master independently of this change (can't find lib burn_ndarray at src/lib.rs), so the edited burn matmul is not compiled anywhere.Provenance
examples/bf16_rne_exhaustive.rs(4019888)0x5cd3eaa07f7f8080(the same with 2 threads), 11.5 s.Docs
README (
d194be7) and README-DE (1dec0d3)f2c1aea: 100 hpc modules, 2,534 lib tests, Rust 1.98.1.Fingerprint<256>is 2,048 B, and TDPBUSD is 16,384 MACs per instruction.Gates run
cargo clippy -p ndarray --features runtime-dispatch --all-targets -- -D warnings: clean.cargo test --lib --features runtime-dispatch -- simd_runtime: 16 passed.scripts/masking-parity.shon native/v4, v3, neon-qemu, wasm and wasm-scalar: all PASS.🤖 Generated with Claude Code
https://claude.ai/code/session_01HdJxpkHATkdNL2veorKao2
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