diff --git a/Alif/AppKit-E7_USB/Board/AppKit-E7_M55_HP/RTE/Device/AE722F80F55D5LS_M55_HP/RTE_Device.h b/Alif/AppKit-E7_USB/Board/AppKit-E7_M55_HP/RTE/Device/AE722F80F55D5LS_M55_HP/RTE_Device.h index 8a31787..c35dc63 100644 --- a/Alif/AppKit-E7_USB/Board/AppKit-E7_M55_HP/RTE/Device/AE722F80F55D5LS_M55_HP/RTE_Device.h +++ b/Alif/AppKit-E7_USB/Board/AppKit-E7_M55_HP/RTE/Device/AE722F80F55D5LS_M55_HP/RTE_Device.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved. +/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved. * Use, distribution and modification of this code is permitted under the * terms stated in the Alif Semiconductor Software License Agreement * @@ -726,6 +726,27 @@ // Default: 0 #define RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG 1 +// MT9M114 MIPI frame width and height(derived from IMAGE_CONFIG) +// defines MT9M114 MIPI frame width & height +// default: 1280x720 +#if (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 0) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 1288 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 728 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 1) || \ + (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 2) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 1280 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 720 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 3) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 640 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 480 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 4) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 320 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 240 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 5) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 320 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 320 +#endif + // select MT9M114 MIPI number of lanes in DPHY // defines select MT9M114 MIPI number of lanes in DPHY. // default: 1 one lane @@ -956,15 +977,39 @@ // default: 2 (IPI-16 RAW 8) #define RTE_OV5675_CAMERA_SENSOR_CPI_COLOR_MODE 2 -// select OV5675 frame height -// defines select OV5675 frame height. +// Select OV5675 image configuration +// <0=> 1296x972_RAW10 +// <1=> 1920x1080_RAW10 +// <2=> 1280x720_RAW10 +// <3=> 640x480_RAW10 +// Default: 0 +#define RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG 0 + +// OV5675 frame height (derived from IMAGE_CONFIG) +// defines OV5675 frame height. // default: 972 +#if (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 1) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 1080 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 2) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 720 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 3) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 480 +#else #define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 972 +#endif -// select OV5675 frame width -// defines select OV5675 frame width. +// OV5675 frame width (derived from IMAGE_CONFIG) +// defines OV5675 frame width. // default: 1296 +#if (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 1) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1920 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 2) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1280 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 3) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 640 +#else #define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1296 +#endif // Select camera sensor OV5675 i2c instance // Defines camera sensor OV5675 i2c instance @@ -7205,6 +7250,29 @@ // Default: ENABLE #define RTE_ADC120_COMPARATOR_BIAS 2 +// ADC120 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC120 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC120_DMA_ENABLE 0 + +// ADC120 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC120_SELECT_DMA0 1 + +// ADC120 DMA IRQ priority <0-255> +// Defines ADC120 DMA interrupt priority +// Default: 0 +#define RTE_ADC120_DMA_IRQ_PRI 0 + +// ADC120 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 4096 +#define RTE_ADC120_DMA_MCODE_SIZE 4096 + #endif // ADC120 (Analog to Digital Converter 0) [Driver_ADC120] @@ -7307,6 +7375,29 @@ // Default: ENABLE #define RTE_ADC121_COMPARATOR_BIAS 2 +// ADC121 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC121 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC121_DMA_ENABLE 0 + +// ADC121 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC121_SELECT_DMA0 1 + +// ADC121 DMA IRQ priority <0-255> +// Defines ADC121 DMA interrupt priority +// Default: 0 +#define RTE_ADC121_DMA_IRQ_PRI 0 + +// ADC121 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 4096 +#define RTE_ADC121_DMA_MCODE_SIZE 4096 + #endif // ADC121 (Analog to Digital Converter 1) [Driver_ADC121] @@ -7409,6 +7500,29 @@ // Default: ENABLE #define RTE_ADC122_COMPARATOR_BIAS 2 +// ADC122 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC122 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC122_DMA_ENABLE 0 + +// ADC122 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC122_SELECT_DMA0 1 + +// ADC122 DMA IRQ priority <0-255> +// Defines ADC122 DMA interrupt priority +// Default: 0 +#define RTE_ADC122_DMA_IRQ_PRI 0 + +// ADC122 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 4096 +#define RTE_ADC122_DMA_MCODE_SIZE 4096 + #endif // ADC122 (Analog to Digital Converter 2) [Driver_ADC122] @@ -7503,6 +7617,29 @@ // Default: 3 #define RTE_ADC24_BIAS (3) +// ADC24 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC24 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC24_DMA_ENABLE 0 + +// ADC24 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC24_SELECT_DMA0 1 + +// ADC24 DMA IRQ priority <0-255> +// Defines ADC24 DMA interrupt priority +// Default: 0 +#define RTE_ADC24_DMA_IRQ_PRI 0 + +// ADC24 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 4096 +#define RTE_ADC24_DMA_MCODE_SIZE 4096 + #endif // ADC24 (Analog to Digital Converter 0) [Driver_ADC24] // ADC (Analog to Digital Converter) @@ -8043,6 +8180,17 @@ // Default: 0 #define RTE_I2C0_RX_FIFO_THRESHOLD 0 +// I2C0 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C0_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C0 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C0_SDA_STUCK_LOW_TIMEOUT 1000000 + + // I2C0 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -8055,6 +8203,12 @@ // Defines I2C0 DMA Interrupt priority // Default: 0 #define RTE_I2C0_DMA_IRQ_PRI 0 + +// I2C0 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C0_DMA_SCRATCH_SIZE 256 #endif #endif @@ -8080,6 +8234,16 @@ // Default: 0 #define RTE_I2C1_RX_FIFO_THRESHOLD 0 +// I2C1 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C1_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C1 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C1_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C1 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -8092,6 +8256,12 @@ // Defines I2C1 DMA Interrupt priority // Default: 0 #define RTE_I2C1_DMA_IRQ_PRI 0 + +// I2C1 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C1_DMA_SCRATCH_SIZE 256 #endif #endif @@ -8117,6 +8287,16 @@ // Default: 0 #define RTE_I2C2_RX_FIFO_THRESHOLD 0 +// I2C2 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C2_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C2 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C2_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C2 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -8129,6 +8309,12 @@ // Defines I2C2 DMA Interrupt priority // Default: 0 #define RTE_I2C2_DMA_IRQ_PRI 0 + +// I2C2 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C2_DMA_SCRATCH_SIZE 256 #endif #endif @@ -8155,6 +8341,16 @@ // Default: 0 #define RTE_I2C3_RX_FIFO_THRESHOLD 0 +// I2C3 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C3_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C3 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C3_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C3 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -8167,6 +8363,12 @@ // Defines I2C3 DMA Interrupt priority // Default: 0 #define RTE_I2C3_DMA_IRQ_PRI 0 + +// I2C3 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C3_DMA_SCRATCH_SIZE 256 #endif #endif @@ -9583,17 +9785,18 @@ // SDC BUS WIDTH SELECT // <0=> BUS_WIDTH_1BIT // <1=> BUS_WIDTH_4BIT +// <2=> BUS_WIDTH_8BIT // Defines SDC0 size of bus width // Default: BUS_WIDTH_4BIT #define RTE_SDC_BUS_WIDTH 1 -// SDC CLOCK SELECT -// <0=> SDC_12_5MHz -// <1=> SDC_25MHz -// <2=> SDC_50MHz -// Defines SDC0 Clock select +// SDC CLOCK SELECT (Hz) +// <12500000=> 12.5MHz +// <25000000=> 25MHz +// <50000000=> 50MHz +// Defines SDC0 Clock frequency in Hz // Default: 25MHz -#define RTE_SDC_CLOCK_SELECT 1 +#define RTE_SDC_CLOCK_SELECT 25000000 // SDC DMA SELECT // <0=> SDMA diff --git a/Alif/AppKit-E7_USB/Board/AppKit-E7_M55_HP/RTE/Device/AE722F80F55D5LS_M55_HP/RTE_Device.h.base@2.2.0 b/Alif/AppKit-E7_USB/Board/AppKit-E7_M55_HP/RTE/Device/AE722F80F55D5LS_M55_HP/RTE_Device.h.base@2.2.1 similarity index 97% rename from Alif/AppKit-E7_USB/Board/AppKit-E7_M55_HP/RTE/Device/AE722F80F55D5LS_M55_HP/RTE_Device.h.base@2.2.0 rename to Alif/AppKit-E7_USB/Board/AppKit-E7_M55_HP/RTE/Device/AE722F80F55D5LS_M55_HP/RTE_Device.h.base@2.2.1 index adcf6e9..43a3aa6 100644 --- a/Alif/AppKit-E7_USB/Board/AppKit-E7_M55_HP/RTE/Device/AE722F80F55D5LS_M55_HP/RTE_Device.h.base@2.2.0 +++ b/Alif/AppKit-E7_USB/Board/AppKit-E7_M55_HP/RTE/Device/AE722F80F55D5LS_M55_HP/RTE_Device.h.base@2.2.1 @@ -1,4 +1,4 @@ -/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved. +/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved. * Use, distribution and modification of this code is permitted under the * terms stated in the Alif Semiconductor Software License Agreement * @@ -726,6 +726,27 @@ // Default: 0 #define RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG 2 +// MT9M114 MIPI frame width and height(derived from IMAGE_CONFIG) +// defines MT9M114 MIPI frame width & height +// default: 1280x720 +#if (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 0) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 1288 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 728 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 1) || \ + (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 2) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 1280 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 720 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 3) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 640 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 480 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 4) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 320 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 240 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 5) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 320 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 320 +#endif + // select MT9M114 MIPI number of lanes in DPHY // defines select MT9M114 MIPI number of lanes in DPHY. // default: 1 one lane @@ -956,15 +977,39 @@ // default: 2 (IPI-16 RAW 8) #define RTE_OV5675_CAMERA_SENSOR_CPI_COLOR_MODE 2 -// select OV5675 frame height -// defines select OV5675 frame height. +// Select OV5675 image configuration +// <0=> 1296x972_RAW10 +// <1=> 1920x1080_RAW10 +// <2=> 1280x720_RAW10 +// <3=> 640x480_RAW10 +// Default: 0 +#define RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG 0 + +// OV5675 frame height (derived from IMAGE_CONFIG) +// defines OV5675 frame height. // default: 972 +#if (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 1) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 1080 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 2) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 720 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 3) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 480 +#else #define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 972 +#endif -// select OV5675 frame width -// defines select OV5675 frame width. +// OV5675 frame width (derived from IMAGE_CONFIG) +// defines OV5675 frame width. // default: 1296 +#if (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 1) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1920 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 2) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1280 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 3) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 640 +#else #define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1296 +#endif // Select camera sensor OV5675 i2c instance // Defines camera sensor OV5675 i2c instance @@ -7205,6 +7250,29 @@ // Default: ENABLE #define RTE_ADC120_COMPARATOR_BIAS 2 +// ADC120 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC120 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC120_DMA_ENABLE 0 + +// ADC120 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC120_SELECT_DMA0 1 + +// ADC120 DMA IRQ priority <0-255> +// Defines ADC120 DMA interrupt priority +// Default: 0 +#define RTE_ADC120_DMA_IRQ_PRI 0 + +// ADC120 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 4096 +#define RTE_ADC120_DMA_MCODE_SIZE 4096 + #endif // ADC120 (Analog to Digital Converter 0) [Driver_ADC120] @@ -7307,6 +7375,29 @@ // Default: ENABLE #define RTE_ADC121_COMPARATOR_BIAS 2 +// ADC121 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC121 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC121_DMA_ENABLE 0 + +// ADC121 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC121_SELECT_DMA0 1 + +// ADC121 DMA IRQ priority <0-255> +// Defines ADC121 DMA interrupt priority +// Default: 0 +#define RTE_ADC121_DMA_IRQ_PRI 0 + +// ADC121 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 4096 +#define RTE_ADC121_DMA_MCODE_SIZE 4096 + #endif // ADC121 (Analog to Digital Converter 1) [Driver_ADC121] @@ -7409,6 +7500,29 @@ // Default: ENABLE #define RTE_ADC122_COMPARATOR_BIAS 2 +// ADC122 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC122 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC122_DMA_ENABLE 0 + +// ADC122 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC122_SELECT_DMA0 1 + +// ADC122 DMA IRQ priority <0-255> +// Defines ADC122 DMA interrupt priority +// Default: 0 +#define RTE_ADC122_DMA_IRQ_PRI 0 + +// ADC122 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 4096 +#define RTE_ADC122_DMA_MCODE_SIZE 4096 + #endif // ADC122 (Analog to Digital Converter 2) [Driver_ADC122] @@ -7503,6 +7617,29 @@ // Default: 3 #define RTE_ADC24_BIAS (3) +// ADC24 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC24 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC24_DMA_ENABLE 0 + +// ADC24 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC24_SELECT_DMA0 1 + +// ADC24 DMA IRQ priority <0-255> +// Defines ADC24 DMA interrupt priority +// Default: 0 +#define RTE_ADC24_DMA_IRQ_PRI 0 + +// ADC24 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 4096 +#define RTE_ADC24_DMA_MCODE_SIZE 4096 + #endif // ADC24 (Analog to Digital Converter 0) [Driver_ADC24] // ADC (Analog to Digital Converter) @@ -8043,6 +8180,17 @@ // Default: 0 #define RTE_I2C0_RX_FIFO_THRESHOLD 0 +// I2C0 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C0_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C0 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C0_SDA_STUCK_LOW_TIMEOUT 1000000 + + // I2C0 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -8055,6 +8203,12 @@ // Defines I2C0 DMA Interrupt priority // Default: 0 #define RTE_I2C0_DMA_IRQ_PRI 0 + +// I2C0 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C0_DMA_SCRATCH_SIZE 256 #endif #endif @@ -8080,6 +8234,16 @@ // Default: 0 #define RTE_I2C1_RX_FIFO_THRESHOLD 0 +// I2C1 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C1_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C1 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C1_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C1 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -8092,6 +8256,12 @@ // Defines I2C1 DMA Interrupt priority // Default: 0 #define RTE_I2C1_DMA_IRQ_PRI 0 + +// I2C1 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C1_DMA_SCRATCH_SIZE 256 #endif #endif @@ -8117,6 +8287,16 @@ // Default: 0 #define RTE_I2C2_RX_FIFO_THRESHOLD 0 +// I2C2 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C2_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C2 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C2_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C2 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -8129,6 +8309,12 @@ // Defines I2C2 DMA Interrupt priority // Default: 0 #define RTE_I2C2_DMA_IRQ_PRI 0 + +// I2C2 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C2_DMA_SCRATCH_SIZE 256 #endif #endif @@ -8155,6 +8341,16 @@ // Default: 0 #define RTE_I2C3_RX_FIFO_THRESHOLD 0 +// I2C3 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C3_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C3 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C3_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C3 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -8167,6 +8363,12 @@ // Defines I2C3 DMA Interrupt priority // Default: 0 #define RTE_I2C3_DMA_IRQ_PRI 0 + +// I2C3 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C3_DMA_SCRATCH_SIZE 256 #endif #endif @@ -9583,17 +9785,18 @@ // SDC BUS WIDTH SELECT // <0=> BUS_WIDTH_1BIT // <1=> BUS_WIDTH_4BIT +// <2=> BUS_WIDTH_8BIT // Defines SDC0 size of bus width // Default: BUS_WIDTH_4BIT #define RTE_SDC_BUS_WIDTH 1 -// SDC CLOCK SELECT -// <0=> SDC_12_5MHz -// <1=> SDC_25MHz -// <2=> SDC_50MHz -// Defines SDC0 Clock select +// SDC CLOCK SELECT (Hz) +// <12500000=> 12.5MHz +// <25000000=> 25MHz +// <50000000=> 50MHz +// Defines SDC0 Clock frequency in Hz // Default: 25MHz -#define RTE_SDC_CLOCK_SELECT 1 +#define RTE_SDC_CLOCK_SELECT 25000000 // SDC DMA SELECT // <0=> SDMA diff --git a/Alif/DevKit-E8_ETH/Board/DevKit-E8_M55_HP/RTE/Device/AE822FA0E5597LS0_M55_HP/RTE_Device.h b/Alif/DevKit-E8_ETH/Board/DevKit-E8_M55_HP/RTE/Device/AE822FA0E5597LS0_M55_HP/RTE_Device.h index cc05564..02d3ef6 100644 --- a/Alif/DevKit-E8_ETH/Board/DevKit-E8_M55_HP/RTE/Device/AE822FA0E5597LS0_M55_HP/RTE_Device.h +++ b/Alif/DevKit-E8_ETH/Board/DevKit-E8_M55_HP/RTE/Device/AE822FA0E5597LS0_M55_HP/RTE_Device.h @@ -374,89 +374,22 @@ // Default: 0 #define RTE_ISP_IRQ_PRIORITY 0 -// ISP Enable AE Module +// ISP Binning Enable // <0=> disable // <1=> enable -// defines if AE Module is enabled or not +// Enable binning processing in ISP // default: false -#define RTE_ISP_AE_MODULE 1 +#define RTE_ISP_BINNING_ENABLE 0 -// ISP Enable BLS Module -// <0=> disable -// <1=> enable -// defines if Black Level Subtraction Module is enabled or not -// default: false -#define RTE_ISP_BLS_MODULE 1 - -// ISP Enable DMSC Module -// <0=> disable -// <1=> enable -// defines if Demosaic Module is enabled or not -// default: false -#define RTE_ISP_DMSC_MODULE 1 - -// ISP Enable FLT Module -// <0=> disable -// <1=> enable -// defines if Noise/Sharpening-Filter Module is enabled or not -// default: false -#define RTE_ISP_FLT_MODULE 1 - -// ISP Enable CCM Module -// <0=> disable -// <1=> enable -// defines if Color Correction Matrix Module is enabled or not -// default: false -#define RTE_ISP_CCM_MODULE 1 - -// ISP Enable CSM Module -// <0=> disable -// <1=> enable -// defines if Color Space Conversion Module is enabled or not -// default: false -#define RTE_ISP_CSM_MODULE 1 - -// ISP Enable WB Module -// <0=> disable -// <1=> enable -// defines if White Balancing Module is enabled or not -// default: false -#define RTE_ISP_WB_MODULE 1 - -// ISP Enable EXPM Module -// <0=> disable -// <1=> enable -// defines if Auto-Exposure Statistics Module is enabled or not -// default: false -#define RTE_ISP_EXPM_MODULE 1 - -// ISP Enable Gamma-out Module -// <0=> disable -// <1=> enable -// defines if Gamma-out Module is enabled or not -// default: false -#define RTE_ISP_GAMMAOUT_MODULE 1 - -// ISP Enable WBM Module -// <0=> disable -// <1=> enable -// defines if White-Balancing Statistics Module is enabled or not -// default: false -#define RTE_ISP_WBM_MODULE 1 - -// ISP Enable Binning Module -// <0=> disable -// <1=> enable -// defines if Binning Module is enabled or not -// default: false -#define RTE_ISP_BINNING_MODULE 1 +// ISP Binning Horizontal Step <0-255> +// Horizontal binning step size +// default: 0 +#define RTE_ISP_BINNING_HSTEP 0 -// ISP Enable Scaling Module -// <0=> disable -// <1=> enable -// defines if scaling Module is enabled or not -// default: true -#define RTE_ISP_SCALAR_MODULE 1 +// ISP Binning Vertical Step <0-255> +// Vertical binning step size +// default: 0 +#define RTE_ISP_BINNING_VSTEP 0 // ISP log level // <0=> NONE @@ -498,36 +431,48 @@ // Height in pixels of the ISP scaler output (after scaling from sensor dimensions). #define RTE_ISP_OUTPUT_HEIGHT 480 -// ISP Sensor Input Width -// Width in pixels of the sensor input to the ISP pipeline. -// Default: MT9M114 sensor resolution (1280). Change for different sensors. -#define RTE_ISP_SENSOR_INPUT_WIDTH RTE_MT9M114_CAMERA_SENSOR_FRAME_WIDTH +#endif +// ISP (ISP) [Driver_ISP] -// ISP Sensor Input Height -// Height in pixels of the sensor input to the ISP pipeline. -// Default: MT9M114 sensor resolution (720). Change for different sensors. -#define RTE_ISP_SENSOR_INPUT_HEIGHT RTE_MT9M114_CAMERA_SENSOR_FRAME_HEIGHT +// JPEG (JPEG) [Driver_JPEG] +// Configuration settings for Driver_JPEG in component ::Drivers:JPEG +#define RTE_JPEG 1 +#if RTE_JPEG -// ISP Crop Top offset <0-4095> -// Top offset in pixels for the cropped output window -#define RTE_ISP_CROP_TOP 0 +// JPEG IRQ priority <0-255> +// Defines Interrupt priority for JPEG. +// Default: 0 +#define RTE_JPEG_IRQ_PRIORITY 0 -// ISP Crop Left offset <0-4095> -// Left offset in pixels for the cropped output window -#define RTE_ISP_CROP_LEFT 0 +// JPEG Encoding Mode +// <0=> 4:2:0(4lum+2chrblocks/MCU) +// Defines encoding mode for JPEG. +// Default: 0 +#define RTE_JPEG_MODE 0 -// ISP Crop Width <1-4095> -// Width in pixels of the cropped output window. -// Default: full sensor input (no crop). Override with smaller value to crop. -#define RTE_ISP_CROP_WIDTH RTE_ISP_SENSOR_INPUT_WIDTH +// JPEG Encoding Mode +// <0=> JPEGENC_420_MODE +// Defines encoding mode for JPEG. +// Default: 0 +#define RTE_JPEG_CODING_MODE 0 -// ISP Crop Height <1-4095> -// Height in pixels of the cropped output window. -// Default: full sensor input (no crop). Override with smaller value to crop. -#define RTE_ISP_CROP_HEIGHT RTE_ISP_SENSOR_INPUT_HEIGHT +// JPEG AXI Burst Length +// AXI burst length for JPEG. +// Default: 64 +#define RTE_JPEG_AXI_BURST_LENGTH 64 + +// JPEG AXI write outstanding number +// AXI write outstanding number for JPEG. +// Default: 64 +#define RTE_AXI_WRITE_OUTSTANDING_NUM 64 + +// JPEG AXI read outstanding number +// AXI read outstanding number for JPEG. +// Default: 64 +#define RTE_AXI_READ_OUTSTANDING_NUM 64 #endif -// ISP (ISP) [Driver_ISP] +// JPEG (JPEG) [Driver_JPEG] // MIPI_CSI2 (mipi csi2) [Driver_MIPI_CSI2] // Configuration settings for Driver_MIPI_CSI2 in component ::Drivers:MIPI_CSI2 @@ -1000,6 +945,27 @@ // Default: 1 #define RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG 1 +// MT9M114 MIPI frame width and height(derived from IMAGE_CONFIG) +// defines MT9M114 MIPI frame width & height +// default: 1280x720 +#if (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 0) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 1288 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 728 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 1) || \ + (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 2) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 1280 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 720 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 3) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 640 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 480 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 4) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 320 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 240 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 5) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 320 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 320 +#endif + // select MT9M114 MIPI number of lanes in DPHY // defines select MT9M114 MIPI number of lanes in DPHY. // default: 1 one lane @@ -1238,15 +1204,39 @@ // default: 2 (IPI-16 RAW 8) #define RTE_OV5675_CAMERA_SENSOR_CPI_COLOR_MODE 2 -// select OV5675 frame height -// defines select OV5675 frame height. +// Select OV5675 image configuration +// <0=> 1296x972_RAW10 +// <1=> 1920x1080_RAW10 +// <2=> 1280x720_RAW10 +// <3=> 640x480_RAW10 +// Default: 0 +#define RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG 0 + +// OV5675 frame height (derived from IMAGE_CONFIG) +// defines OV5675 frame height. // default: 972 +#if (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 1) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 1080 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 2) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 720 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 3) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 480 +#else #define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 972 +#endif -// select OV5675 frame width -// defines select OV5675 frame width. +// OV5675 frame width (derived from IMAGE_CONFIG) +// defines OV5675 frame width. // default: 1296 +#if (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 1) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1920 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 2) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1280 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 3) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 640 +#else #define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1296 +#endif // Select camera sensor OV5675 i2c instance // Defines camera sensor OV5675 i2c instance @@ -8180,6 +8170,29 @@ // Default: ENABLE #define RTE_ADC120_COMPARATOR_BIAS 2 +// ADC120 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC120 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC120_DMA_ENABLE 0 + +// ADC120 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC120_SELECT_DMA0 1 + +// ADC120 DMA IRQ priority <0-255> +// Defines ADC120 DMA interrupt priority +// Default: 0 +#define RTE_ADC120_DMA_IRQ_PRI 0 + +// ADC120 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 256 +#define RTE_ADC120_DMA_MCODE_SIZE 256 + #endif // ADC120 (Analog to Digital Converter 0) [Driver_ADC120] @@ -8282,6 +8295,29 @@ // Default: ENABLE #define RTE_ADC121_COMPARATOR_BIAS 2 +// ADC121 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC121 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC121_DMA_ENABLE 0 + +// ADC121 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC121_SELECT_DMA0 1 + +// ADC121 DMA IRQ priority <0-255> +// Defines ADC121 DMA interrupt priority +// Default: 0 +#define RTE_ADC121_DMA_IRQ_PRI 0 + +// ADC121 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 256 +#define RTE_ADC121_DMA_MCODE_SIZE 256 + #endif // ADC121 (Analog to Digital Converter 1) [Driver_ADC121] @@ -8384,6 +8420,29 @@ // Default: ENABLE #define RTE_ADC122_COMPARATOR_BIAS 2 +// ADC122 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC122 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC122_DMA_ENABLE 0 + +// ADC122 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC122_SELECT_DMA0 1 + +// ADC122 DMA IRQ priority <0-255> +// Defines ADC122 DMA interrupt priority +// Default: 0 +#define RTE_ADC122_DMA_IRQ_PRI 0 + +// ADC122 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 256 +#define RTE_ADC122_DMA_MCODE_SIZE 256 + #endif // ADC122 (Analog to Digital Converter 2) [Driver_ADC122] @@ -8478,6 +8537,29 @@ // Default: 3 #define RTE_ADC24_BIAS (3) +// ADC24 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC24 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC24_DMA_ENABLE 0 + +// ADC24 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC24_SELECT_DMA0 1 + +// ADC24 DMA IRQ priority <0-255> +// Defines ADC24 DMA interrupt priority +// Default: 0 +#define RTE_ADC24_DMA_IRQ_PRI 0 + +// ADC24 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 256 +#define RTE_ADC24_DMA_MCODE_SIZE 256 + #endif // ADC24 (Analog to Digital Converter 0) [Driver_ADC24] // ADC (Analog to Digital Converter) @@ -9018,6 +9100,16 @@ // Default: 0 #define RTE_I2C0_RX_FIFO_THRESHOLD 0 +// I2C0 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C0_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C0 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C0_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C0 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9030,6 +9122,12 @@ // Defines I2C0 DMA Interrupt priority // Default: 0 #define RTE_I2C0_DMA_IRQ_PRI 0 + +// I2C0 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C0_DMA_SCRATCH_SIZE 256 #endif #endif @@ -9055,6 +9153,16 @@ // Default: 0 #define RTE_I2C1_RX_FIFO_THRESHOLD 0 +// I2C1 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C1_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C1 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C1_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C1 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9067,6 +9175,12 @@ // Defines I2C1 DMA Interrupt priority // Default: 0 #define RTE_I2C1_DMA_IRQ_PRI 0 + +// I2C1 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C1_DMA_SCRATCH_SIZE 256 #endif #endif @@ -9092,6 +9206,16 @@ // Default: 0 #define RTE_I2C2_RX_FIFO_THRESHOLD 0 +// I2C2 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C2_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C2 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C2_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C2 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9104,6 +9228,12 @@ // Defines I2C2 DMA Interrupt priority // Default: 0 #define RTE_I2C2_DMA_IRQ_PRI 0 + +// I2C2 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C2_DMA_SCRATCH_SIZE 256 #endif #endif @@ -9130,6 +9260,16 @@ // Default: 0 #define RTE_I2C3_RX_FIFO_THRESHOLD 0 +// I2C3 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C3_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C3 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C3_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C3 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9142,6 +9282,12 @@ // Defines I2C3 DMA Interrupt priority // Default: 0 #define RTE_I2C3_DMA_IRQ_PRI 0 + +// I2C3 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C3_DMA_SCRATCH_SIZE 256 #endif #endif @@ -9187,6 +9333,16 @@ // Default: 0 #define RTE_LPI2C1_RX_FIFO_THRESHOLD 0 +// LPI2C1 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 160MHz) +#define RTE_LPI2C1_SCL_STUCK_LOW_TIMEOUT 1600000 + +// LPI2C1 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 160MHz) +#define RTE_LPI2C1_SDA_STUCK_LOW_TIMEOUT 1600000 + // LPI2C1 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9199,6 +9355,12 @@ // Defines LPI2C1 DMA Interrupt priority // Default: 0 #define RTE_LPI2C1_DMA_IRQ_PRI 0 + +// LPI2C1 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_LPI2C1_DMA_SCRATCH_SIZE 256 #endif #endif @@ -10786,17 +10948,18 @@ // SDC BUS WIDTH SELECT // <0=> BUS_WIDTH_1BIT // <1=> BUS_WIDTH_4BIT +// <2=> BUS_WIDTH_8BIT // Defines SDC0 size of bus width // Default: BUS_WIDTH_4BIT #define RTE_SDC_BUS_WIDTH 1 -// SDC CLOCK SELECT -// <0=> SDC_12_5MHz -// <1=> SDC_25MHz -// <2=> SDC_50MHz -// Defines SDC0 Clock select +// SDC CLOCK SELECT (Hz) +// <12500000=> 12.5MHz +// <25000000=> 25MHz +// <50000000=> 50MHz +// Defines SDC0 Clock frequency in Hz // Default: 25MHz -#define RTE_SDC_CLOCK_SELECT 1 +#define RTE_SDC_CLOCK_SELECT 25000000 // SDC DMA SELECT // <0=> SDMA diff --git a/Alif/DevKit-E8_ETH/Board/DevKit-E8_M55_HP/RTE/Device/AE822FA0E5597LS0_M55_HP/RTE_Device.h.base@2.2.0 b/Alif/DevKit-E8_ETH/Board/DevKit-E8_M55_HP/RTE/Device/AE822FA0E5597LS0_M55_HP/RTE_Device.h.base@2.2.1 similarity index 96% rename from Alif/DevKit-E8_ETH/Board/DevKit-E8_M55_HP/RTE/Device/AE822FA0E5597LS0_M55_HP/RTE_Device.h.base@2.2.0 rename to Alif/DevKit-E8_ETH/Board/DevKit-E8_M55_HP/RTE/Device/AE822FA0E5597LS0_M55_HP/RTE_Device.h.base@2.2.1 index 70cd1c8..a68b39b 100644 --- a/Alif/DevKit-E8_ETH/Board/DevKit-E8_M55_HP/RTE/Device/AE822FA0E5597LS0_M55_HP/RTE_Device.h.base@2.2.0 +++ b/Alif/DevKit-E8_ETH/Board/DevKit-E8_M55_HP/RTE/Device/AE822FA0E5597LS0_M55_HP/RTE_Device.h.base@2.2.1 @@ -374,89 +374,22 @@ // Default: 0 #define RTE_ISP_IRQ_PRIORITY 0 -// ISP Enable AE Module +// ISP Binning Enable // <0=> disable // <1=> enable -// defines if AE Module is enabled or not +// Enable binning processing in ISP // default: false -#define RTE_ISP_AE_MODULE 1 +#define RTE_ISP_BINNING_ENABLE 0 -// ISP Enable BLS Module -// <0=> disable -// <1=> enable -// defines if Black Level Subtraction Module is enabled or not -// default: false -#define RTE_ISP_BLS_MODULE 1 - -// ISP Enable DMSC Module -// <0=> disable -// <1=> enable -// defines if Demosaic Module is enabled or not -// default: false -#define RTE_ISP_DMSC_MODULE 1 - -// ISP Enable FLT Module -// <0=> disable -// <1=> enable -// defines if Noise/Sharpening-Filter Module is enabled or not -// default: false -#define RTE_ISP_FLT_MODULE 1 - -// ISP Enable CCM Module -// <0=> disable -// <1=> enable -// defines if Color Correction Matrix Module is enabled or not -// default: false -#define RTE_ISP_CCM_MODULE 1 - -// ISP Enable CSM Module -// <0=> disable -// <1=> enable -// defines if Color Space Conversion Module is enabled or not -// default: false -#define RTE_ISP_CSM_MODULE 1 - -// ISP Enable WB Module -// <0=> disable -// <1=> enable -// defines if White Balancing Module is enabled or not -// default: false -#define RTE_ISP_WB_MODULE 1 - -// ISP Enable EXPM Module -// <0=> disable -// <1=> enable -// defines if Auto-Exposure Statistics Module is enabled or not -// default: false -#define RTE_ISP_EXPM_MODULE 1 - -// ISP Enable Gamma-out Module -// <0=> disable -// <1=> enable -// defines if Gamma-out Module is enabled or not -// default: false -#define RTE_ISP_GAMMAOUT_MODULE 1 - -// ISP Enable WBM Module -// <0=> disable -// <1=> enable -// defines if White-Balancing Statistics Module is enabled or not -// default: false -#define RTE_ISP_WBM_MODULE 1 - -// ISP Enable Binning Module -// <0=> disable -// <1=> enable -// defines if Binning Module is enabled or not -// default: false -#define RTE_ISP_BINNING_MODULE 1 +// ISP Binning Horizontal Step <0-255> +// Horizontal binning step size +// default: 0 +#define RTE_ISP_BINNING_HSTEP 0 -// ISP Enable Scaling Module -// <0=> disable -// <1=> enable -// defines if scaling Module is enabled or not -// default: true -#define RTE_ISP_SCALAR_MODULE 1 +// ISP Binning Vertical Step <0-255> +// Vertical binning step size +// default: 0 +#define RTE_ISP_BINNING_VSTEP 0 // ISP log level // <0=> NONE @@ -498,36 +431,48 @@ // Height in pixels of the ISP scaler output (after scaling from sensor dimensions). #define RTE_ISP_OUTPUT_HEIGHT 480 -// ISP Sensor Input Width -// Width in pixels of the sensor input to the ISP pipeline. -// Default: MT9M114 sensor resolution (1280). Change for different sensors. -#define RTE_ISP_SENSOR_INPUT_WIDTH RTE_MT9M114_CAMERA_SENSOR_FRAME_WIDTH +#endif +// ISP (ISP) [Driver_ISP] -// ISP Sensor Input Height -// Height in pixels of the sensor input to the ISP pipeline. -// Default: MT9M114 sensor resolution (720). Change for different sensors. -#define RTE_ISP_SENSOR_INPUT_HEIGHT RTE_MT9M114_CAMERA_SENSOR_FRAME_HEIGHT +// JPEG (JPEG) [Driver_JPEG] +// Configuration settings for Driver_JPEG in component ::Drivers:JPEG +#define RTE_JPEG 1 +#if RTE_JPEG -// ISP Crop Top offset <0-4095> -// Top offset in pixels for the cropped output window -#define RTE_ISP_CROP_TOP 0 +// JPEG IRQ priority <0-255> +// Defines Interrupt priority for JPEG. +// Default: 0 +#define RTE_JPEG_IRQ_PRIORITY 0 -// ISP Crop Left offset <0-4095> -// Left offset in pixels for the cropped output window -#define RTE_ISP_CROP_LEFT 0 +// JPEG Encoding Mode +// <0=> 4:2:0(4lum+2chrblocks/MCU) +// Defines encoding mode for JPEG. +// Default: 0 +#define RTE_JPEG_MODE 0 -// ISP Crop Width <1-4095> -// Width in pixels of the cropped output window. -// Default: full sensor input (no crop). Override with smaller value to crop. -#define RTE_ISP_CROP_WIDTH RTE_ISP_SENSOR_INPUT_WIDTH +// JPEG Encoding Mode +// <0=> JPEGENC_420_MODE +// Defines encoding mode for JPEG. +// Default: 0 +#define RTE_JPEG_CODING_MODE 0 -// ISP Crop Height <1-4095> -// Height in pixels of the cropped output window. -// Default: full sensor input (no crop). Override with smaller value to crop. -#define RTE_ISP_CROP_HEIGHT RTE_ISP_SENSOR_INPUT_HEIGHT +// JPEG AXI Burst Length +// AXI burst length for JPEG. +// Default: 64 +#define RTE_JPEG_AXI_BURST_LENGTH 64 + +// JPEG AXI write outstanding number +// AXI write outstanding number for JPEG. +// Default: 64 +#define RTE_AXI_WRITE_OUTSTANDING_NUM 64 + +// JPEG AXI read outstanding number +// AXI read outstanding number for JPEG. +// Default: 64 +#define RTE_AXI_READ_OUTSTANDING_NUM 64 #endif -// ISP (ISP) [Driver_ISP] +// JPEG (JPEG) [Driver_JPEG] // MIPI_CSI2 (mipi csi2) [Driver_MIPI_CSI2] // Configuration settings for Driver_MIPI_CSI2 in component ::Drivers:MIPI_CSI2 @@ -1000,6 +945,27 @@ // Default: 1 #define RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG 1 +// MT9M114 MIPI frame width and height(derived from IMAGE_CONFIG) +// defines MT9M114 MIPI frame width & height +// default: 1280x720 +#if (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 0) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 1288 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 728 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 1) || \ + (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 2) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 1280 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 720 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 3) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 640 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 480 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 4) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 320 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 240 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 5) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 320 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 320 +#endif + // select MT9M114 MIPI number of lanes in DPHY // defines select MT9M114 MIPI number of lanes in DPHY. // default: 1 one lane @@ -1238,15 +1204,39 @@ // default: 2 (IPI-16 RAW 8) #define RTE_OV5675_CAMERA_SENSOR_CPI_COLOR_MODE 2 -// select OV5675 frame height -// defines select OV5675 frame height. +// Select OV5675 image configuration +// <0=> 1296x972_RAW10 +// <1=> 1920x1080_RAW10 +// <2=> 1280x720_RAW10 +// <3=> 640x480_RAW10 +// Default: 0 +#define RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG 0 + +// OV5675 frame height (derived from IMAGE_CONFIG) +// defines OV5675 frame height. // default: 972 +#if (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 1) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 1080 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 2) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 720 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 3) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 480 +#else #define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 972 +#endif -// select OV5675 frame width -// defines select OV5675 frame width. +// OV5675 frame width (derived from IMAGE_CONFIG) +// defines OV5675 frame width. // default: 1296 +#if (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 1) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1920 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 2) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1280 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 3) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 640 +#else #define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1296 +#endif // Select camera sensor OV5675 i2c instance // Defines camera sensor OV5675 i2c instance @@ -8180,6 +8170,29 @@ // Default: ENABLE #define RTE_ADC120_COMPARATOR_BIAS 2 +// ADC120 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC120 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC120_DMA_ENABLE 0 + +// ADC120 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC120_SELECT_DMA0 1 + +// ADC120 DMA IRQ priority <0-255> +// Defines ADC120 DMA interrupt priority +// Default: 0 +#define RTE_ADC120_DMA_IRQ_PRI 0 + +// ADC120 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 256 +#define RTE_ADC120_DMA_MCODE_SIZE 256 + #endif // ADC120 (Analog to Digital Converter 0) [Driver_ADC120] @@ -8282,6 +8295,29 @@ // Default: ENABLE #define RTE_ADC121_COMPARATOR_BIAS 2 +// ADC121 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC121 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC121_DMA_ENABLE 0 + +// ADC121 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC121_SELECT_DMA0 1 + +// ADC121 DMA IRQ priority <0-255> +// Defines ADC121 DMA interrupt priority +// Default: 0 +#define RTE_ADC121_DMA_IRQ_PRI 0 + +// ADC121 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 256 +#define RTE_ADC121_DMA_MCODE_SIZE 256 + #endif // ADC121 (Analog to Digital Converter 1) [Driver_ADC121] @@ -8384,6 +8420,29 @@ // Default: ENABLE #define RTE_ADC122_COMPARATOR_BIAS 2 +// ADC122 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC122 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC122_DMA_ENABLE 0 + +// ADC122 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC122_SELECT_DMA0 1 + +// ADC122 DMA IRQ priority <0-255> +// Defines ADC122 DMA interrupt priority +// Default: 0 +#define RTE_ADC122_DMA_IRQ_PRI 0 + +// ADC122 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 256 +#define RTE_ADC122_DMA_MCODE_SIZE 256 + #endif // ADC122 (Analog to Digital Converter 2) [Driver_ADC122] @@ -8478,6 +8537,29 @@ // Default: 3 #define RTE_ADC24_BIAS (3) +// ADC24 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC24 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC24_DMA_ENABLE 0 + +// ADC24 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC24_SELECT_DMA0 1 + +// ADC24 DMA IRQ priority <0-255> +// Defines ADC24 DMA interrupt priority +// Default: 0 +#define RTE_ADC24_DMA_IRQ_PRI 0 + +// ADC24 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 256 +#define RTE_ADC24_DMA_MCODE_SIZE 256 + #endif // ADC24 (Analog to Digital Converter 0) [Driver_ADC24] // ADC (Analog to Digital Converter) @@ -9018,6 +9100,16 @@ // Default: 0 #define RTE_I2C0_RX_FIFO_THRESHOLD 0 +// I2C0 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C0_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C0 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C0_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C0 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9030,6 +9122,12 @@ // Defines I2C0 DMA Interrupt priority // Default: 0 #define RTE_I2C0_DMA_IRQ_PRI 0 + +// I2C0 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C0_DMA_SCRATCH_SIZE 256 #endif #endif @@ -9055,6 +9153,16 @@ // Default: 0 #define RTE_I2C1_RX_FIFO_THRESHOLD 0 +// I2C1 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C1_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C1 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C1_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C1 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9067,6 +9175,12 @@ // Defines I2C1 DMA Interrupt priority // Default: 0 #define RTE_I2C1_DMA_IRQ_PRI 0 + +// I2C1 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C1_DMA_SCRATCH_SIZE 256 #endif #endif @@ -9092,6 +9206,16 @@ // Default: 0 #define RTE_I2C2_RX_FIFO_THRESHOLD 0 +// I2C2 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C2_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C2 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C2_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C2 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9104,6 +9228,12 @@ // Defines I2C2 DMA Interrupt priority // Default: 0 #define RTE_I2C2_DMA_IRQ_PRI 0 + +// I2C2 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C2_DMA_SCRATCH_SIZE 256 #endif #endif @@ -9130,6 +9260,16 @@ // Default: 0 #define RTE_I2C3_RX_FIFO_THRESHOLD 0 +// I2C3 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C3_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C3 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C3_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C3 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9142,6 +9282,12 @@ // Defines I2C3 DMA Interrupt priority // Default: 0 #define RTE_I2C3_DMA_IRQ_PRI 0 + +// I2C3 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C3_DMA_SCRATCH_SIZE 256 #endif #endif @@ -9187,6 +9333,16 @@ // Default: 0 #define RTE_LPI2C1_RX_FIFO_THRESHOLD 0 +// LPI2C1 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 160MHz) +#define RTE_LPI2C1_SCL_STUCK_LOW_TIMEOUT 1600000 + +// LPI2C1 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 160MHz) +#define RTE_LPI2C1_SDA_STUCK_LOW_TIMEOUT 1600000 + // LPI2C1 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9199,6 +9355,12 @@ // Defines LPI2C1 DMA Interrupt priority // Default: 0 #define RTE_LPI2C1_DMA_IRQ_PRI 0 + +// LPI2C1 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_LPI2C1_DMA_SCRATCH_SIZE 256 #endif #endif @@ -10786,17 +10948,18 @@ // SDC BUS WIDTH SELECT // <0=> BUS_WIDTH_1BIT // <1=> BUS_WIDTH_4BIT +// <2=> BUS_WIDTH_8BIT // Defines SDC0 size of bus width // Default: BUS_WIDTH_4BIT #define RTE_SDC_BUS_WIDTH 1 -// SDC CLOCK SELECT -// <0=> SDC_12_5MHz -// <1=> SDC_25MHz -// <2=> SDC_50MHz -// Defines SDC0 Clock select +// SDC CLOCK SELECT (Hz) +// <12500000=> 12.5MHz +// <25000000=> 25MHz +// <50000000=> 50MHz +// Defines SDC0 Clock frequency in Hz // Default: 25MHz -#define RTE_SDC_CLOCK_SELECT 1 +#define RTE_SDC_CLOCK_SELECT 25000000 // SDC DMA SELECT // <0=> SDMA